1. Field of the Invention
This invention relates to a semiconductor memory device of the type having a one-transistor/one-cell structure as formed on a silicon-on-insulator (SOI) substrate.
2. Description of Related Art
Recently, for the purpose of alternative use or replacement of conventional dynamic random access memory (DRAM) devices, a semiconductor memory device that has a more simplified cell structure for enabling achievement of dynamic storability has been proposed. This type of memory is disclosed, for example, in Takashi Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, 2002, pp. 152–153.
A memory cell is structured from a single transistor which has an electrically floating body (channel body) as formed on a silicon-on-insulator (SOI) substrate. This memory cell offers two-value data storing capabilities while regarding the state that an excess number of majority carriers are accumulated or stored in the body as a first data state (for example, logic “1” data) and letting the state that the excessive majority carriers are drawn out from the body be as a second data state (e.g. logic “0” data).
The one-transistor memory cell of the type stated above will be referred to hereinafter as a floating-body cell (FBC). A semiconductor memory using FBCs will be called the “FBC memory”. The FBC memory makes use of no capacitors unlike currently available standard DRAM chips so that this one-transistor/no-capacitor or “capacitor-less” cell memory is, simpler in memory cell array structure and smaller in unit cell area than ever before. Thus FBC memory is readily scalable in cell structure and advantageously offers much enhanced on-chip integration capabilities.
For writing logic “1” data in the FBC memory, impact ionization near the drain of a memory cell is utilized. More specifically, giving appropriate bias conditions for permitting flow of a significant channel current in the memory cell, causes majority carriers that are produced by impact ionization to be stored in the floating body. Writing logic “0” data is performed by setting a PN junction between the drain and the body in a forward bias state to thereby release the body's majority carriers toward the drain side.
A difference in the carrier storage states of such floating body appears as a difference in threshold voltage of a transistor. Thus it is possible to determine or sense whether the resultant read data is a logic “0” or “1” by detecting whether an appreciable cell current is present or absent, alternatively, whether the cell current is large or small in magnitude, while applying a prespecified read voltage to the gate of a presently selected memory cell. Excess majority carriers of the body would be drawn out through the PN junctions between the source, drain and the body when letting the cell be unprocessed for an increased length of time period. Thus a need is felt to perform refresh operations at constant time intervals as in ordinary DRAMs.
For improving the characteristics of the FBC memory, it has also been proposed to employ in addition to the main gate of a memory cell an auxiliary gate which is capacitively coupled to the floating body. This approach has been disclosed, for example, in Published Japanese Patent Application Nos. 2002-246571 and 2003-31693.
The FBC memory is provided for replacing the conventional DRAM. For this purpose, it is required of the FBC memory to have high-speed performance as being equal to or higher than that of the conventional DRAM. However, the bit line of the FBC memory must be held at a low level during reading in order to prevent impact ionization. Due to this, it is not easy to flow a large cell current, thereby resulting that it is not easy to obtain high-sensitivity. If impossible to flow a large cell current, it takes a long time period for charging/discharging the bit line connected to a memory cell, whereby it becomes impossible to perform high-speed read operation.